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SMM766
Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link
Preliminary Information 1 (See Last Page)
FEATURES & APPLICATIONS
* Extremely accurate (0.2%) Active DC Output Control (ADOCTM) * Sequence-LinkTM provides sequencing of up to 48 channels * ADOC automatically adjusts supply output voltage level under all DC load conditions * Monitors, controls, and margins up to 6 supplies from 0.3V to 5.5V with 1.25V Vref * Programmable power-on/-off sequencing * Operates from any intermediate bus supply from 6V to 14V and from 2.7V to 5.5V * Monitors 12V input VDD and temperature sensor * Wide margin/ADOC range from 0.3V to VDD * Monitors two general-purpose 10-bit ADC inputs * I2C 2-wire serial bus for programming configuration and monitoring status, including 10-bit ADC conversion results * 2 programmable Under Voltage (UV) and Over Voltage (OV) threshold limits for each of 11 monitored inputs * 2k-bit general purpose nonvolatile memory Applications * Monitor/control distributed and POL supplies * Multi-voltage processors, DSPs, ASICSs used in telecom, CompactPCI or server systems
INTRODUCTION
The SMM766 is an Active DC Output power supply Controller (ADOCTM) that monitors, margins, and cascade sequences. The ADOC feature is unique and maintains extremely accurate settings of system supply voltages to within 0.2% under full load. The SMM766 actively controls up to 6 DC/DC converters and can be linked with up to 7 other Sequence-LinkTM devices to accommodate sequencing of up to 48 channels. Control of the DC-DC converters is accomplished through the use of a Trim or Regulator VADJ/FB pin to adjust the output voltage. For system test, the part also controls margining of the supplies using I2C commands. It can margin supplies with either positive or negative control within a range of 0.3V to VDD, depending on the specified range of the converter. The SMM766 also intelligently sequences or cascades the power supplies on and off in any order using enable outputs with programmable polarity. It can operate off any intermediate bus supply ranging from 6V to 14V or from 5.5V to as low as 2.7V. The part monitors 6 power supply channels as well as VDD, 12V input, two general-purpose analog inputs and an internal temperature sensor using a 10-bit ADC. The 10-bit ADC can measure the value on any one of the monitor channels and output the data via the I2C bus. A host system can communicate with the SMM766 status register, margining and utilize 2K-bits of nonvolatile memory.
SIMPLIFIED APPLICATIONS DRAWING
12VIN (+6V to +14V Range) 3.3VIN (+2.7V to +5.5V Range)
12VIN VDD CAPA TRIM_CAPA SDA SCL A2 SEQ_LINK External or Internal TEMP SENSOR TRIMA PUPA VMA CAPB TRIM_CAPB AIN2 HEALTHY VREF MR# 2 of 6 DC-DC Converters shown
DC/DC Converter D, F VIN DC/DC Converter B Vout TRIM ON/OFF
12V
DC/DC Converter C, E VIN DC/DC Converter A Vout TRIM ON/OFF
3.3V
To additional SequenceLink devices
I2C BUS
2.5VIN
SMM766
AIN1
P/ ASIC
1.2VIN
Environmental SENSOR External or Internal REFERENCE
TRIMB PUPB RST# VMB
HEALTHY
RESET# READY
Figure 1 - Applications schematic using the SMM766 controller to actively control the output levels of up to 6 DC/DC converters while also providing power-on/off, cascade sequencing and output margining.
Note: This is an applications example only. Some pins, components and values are not shown. (c) SUMMIT Microelectronics, Inc. 2004 * 1717 Fox Drive * San Jose CA 95131 * Phone 408 436-9890 * FAX 408 436-9897
The Summit Web Site can be accessed by "right" or "left" mouse clicking on the link: http://www.summitmicro.com/
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SMM766
Preliminary Information
TABLE OF CONTENTS
General Description................................. ............3 Internal Functional Block Diagram........... ...............4 Pin Descriptions...............................................5-6 Package And Pin Configuration..................... ........7 Absolute Maximum Ratings..................... .............8 Recommended Operating Conditions......... .............8 DC Operating Characteristics....................... .....8-10 AC Operating Characteristics........................ .......10 I2C 2-Wire Serial Interface AC Operating Characteristics-100/400khz.................................11 Timing Diagrams........................... ...............11-12 DEVICE OPERATION Power Supply........................................................ ....14 Modes Of Operation.................................... .......14 Active DC Output Control........................... ....14-15 Power-On Cascade Sequencing...........................15 Ongoing Operations-Monitoring Mode......... ...........16 Temperature Sensor Accuracy.............................16 Margining................................................... .....17 Power-Off Cascade Sequencing............... ............17 Force-Shutdown........................................... ....17 Linked Operation............................................ ...18 Restart......................................................... ...18 I2C Power-Off Control.................................... .....18 Recommended Use Of The Power On Pin......... ....19 Applications Schematic................................. .....20 Development Hardware & Software............ ...........21 I2C Programming Information Serial Interface..................................................22 Write....................................................... ........22 Read....................................................... .......22 Write Protection............................................ ....23 Configuration Registers................................... ...23 General-Purpose Memory............................... ....23 Command And Status Registers...........................23 ADC Conversions.......................................... ....23 Graphical User Interface (GUI).............................23 Write Protection Register Write........................ .....24 Configuration Register Read/Write............... .....24-25 General-Purpose Memory Read/Write.............. .....26 Command And Status Register Read/Write...... ......27 ADC Conversion Read............................... ........27 Default Configuration Register Settings.......... ........28 Package..................................................... .....29 Part Marking................................................ .....30 Ordering Information.................................... ......30 Terminology And Definitions........................... .....31 Legal Notice.....................................................32
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SMM766
Preliminary Information
SEQUENCE POSITION VDD (+2.7V to +5.5V) or 12VIN ( +8V to +15V) 2.7V 2.5V 2.0V 1.8V 1.5V 1.2V 1 2 3 4 5
Figure 2 - Example power supply sequencing and system start-up initialization using the SMM766. Cascade sequencing ensures that all supplies in the previous sequence position are valid before the next channel is released. Using the SMM766 any order of supply sequencing can be applied.
GENERAL DESCRIPTION
The SMM766 is a highly integrated and accurate power supply controller, monitor, and sequencer. Each device has the ability to automatically control, monitor and cascade sequence up to 6 power supplies. In addition, the SMM766 includes Sequence-Link a feature that allows for the seamless integration of other Sequence-Link devices to accommodate sequencing of up to 48 channels. The SMM766 can monitor the VDD input, the 12V input, two generalpurpose analog inputs, and the internal temperature sensor. The SMM766 has four operating modes: power-on sequencing mode, monitor mode, supply margining mode using Active DC Output Control (ADOCTM), and power-off sequencing mode. Power-on sequencing is initiated by the rising edge of the PWR_ON pin. During power-on sequencing the SMM766 will sequence the power supply channels on, in any order, by activating the PUP outputs and monitoring the respective converter voltages to ensure cascading of the supplies. Cascade sequencing is the ability to hold off the next sequenced supply until the first supply reaches a programmed threshold. A programmable sequence termination timer can be set to disable all channels if the power-on sequence stalls. Once all supplies have sequenced on and the voltages are above the UV settings, the ADOC, if enabled, will bring the supply voltages to their nominal settings. During this mode, the HEALTHY output will remain inactive and the RST# output will remain active. Once the power-on sequencing mode is complete, the SMM766 enters monitor mode. In the monitor mode, the SMM766 starts the ADOC control of the supplies and adjusts the output voltage to the programmed setting under all load conditions, especially useful for supplies without sense lines. Typical converters have 2% accuracy ratings for their output voltage; the ADOC feature of the SMM766 increases the accuracy to 0.2% (using a 0.1% external voltage reference). The part also enables the triggering of outputs by monitored fault conditions. The 10-bit ADC cycles through all 11 channels every 2ms and checks the conversions against the programmed threshold limits. The results can be used to trigger RST#, HEALTHY and FAULT# outputs as well as to initiate a FaultTriggered power-off or force-shutdown operation. While the SMM766 is in its monitoring mode, an I2C command to margin the supply voltages can bring the part into margining mode. In margining mode the SMM766 can margin 6 supply voltages in any combination of nominal, high and low voltage settings using the ADOC feature, all to within 0.2% using a 0.1% external reference. The margin high and low voltage settings can range from 0.3V to VDD around the converters' nominal output voltage setting depending on the specified margin range of the DCDC converter. During this mode the HEALTHY output is always active and the RST# output is always inactive regardless of the voltage threshold limit settings and triggers. Furthermore, the triggers for power-off and force-shutdown are temporarily disabled. The power-off sequencing mode can only be entered while the SMM766 is in the monitoring mode. It can be initiated by either bringing the PWR_ON pin low, through I2C control, or triggered by a channel exceeding its programmed thresholds. Once poweroff is initiated, it will disable the ADOC function and sequence the PUP outputs off in the reverse order as power-on sequencing. To ensure cascading of the supplies during power-off sequencing all supplies will be monitored as they turn off. The sequence termination timer performs a forced-shutdown operation if power-off sequencing stalls.
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SMM766
Preliminary Information
INTERNAL FUNCTIONAL BLOCK DIAGRAM
12VIN VDD VDD_CAP PWR_ON FS#
3.6V or 5.5V Regulator
AIN1 AIN2 VM A CAPA
Power Supply Arbitrator Cascade Sequence Control
SEQ_LINK PUPA PUPB PUPC PUPD PUPE PUPF
10-Bit ADC
Temperature Sensor
UVLO Control
VM F MR# CAPF RST# HEALTHY FAULT# TRIM A TRIM_CAPA
Output Control
TRIM F TRIM_CAPF VREF FILT_CAP
Active DC Output Control (ADOCTM )
Memory, Limit and Status Registers
SDA
IC Interface
2
SCL A2
GND
Figure 3 - SMM766 Internal Functional Block Diagram.
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Preliminary Information
PIN DESCRIPTIONS
Pin Number 1 2 3 Pin Type DATA CLK IN Pin Name SDA SCL A2 Pin Description SDA (Serial Data) is an open drain bi-directional pin used as the I2C data line. SCL (Serial Clock) is an open drain input pin used as the I2C Clock line. The A2 (Address bit 2) pin is biased either to VDD_CAP or GND. When communicating with the SMM766 over the 2-wire I2C bus, A2 provides a mechanism for assigning a unique bus address. MR# (Manual Reset) is an active low input. When asserted the RST# output will become active. When de-asserted the RST# output will go inactive immediately after a reset timeout period (tRTO) if there are no RST# trigger sources active. This timeout period makes it suitable to use as a pushbutton for manual reset purposes. PWR_ON (Power On) is an open drain bi-directional pin. On the rising edge of PWR_ON the part will sequence the supplies on, during the falling edge the part will sequence the supplies off. This pin must be tied high through an external pull-up resistor. Note: The SMM766 does not monitor for faults during power-on/off sequencing. FS# (Force Shutdown) is an open drain active low bi-directional pin. FS# is used to immediately turn off all converter enable signals (PUP outputs) when a fault is detected. Whenever FS# is asserted PWR_ON will automatically be pulled low as well. This pin must be tied high through an external pull-up resistor. The FAULT# pin is an active low open drain output. Active when a programmed fault condition exists on AIN1, AIN2, or the internal temperature sensor. When used, FAULT# should be pulled high through an external pullup resister. HEALTHY is an active high open drain output. Active when all programmed power supply inputs and monitored inputs are within OV and UV limits and ADOC has begun. When used, HEALTHY should be pulled high through an external pull-up resistor. RST# (Reset) is an active low open drain output pin. Active when a programmed fault condition exists on any power supply inputs or monitored inputs, when MR# is active, or when ADOC is not ready. RST# has a programmable timeout period with options for 0.64ms, 25ms, 100ms and 200ms. When used, RST# should be pulled high through an external pull-up resistor. AIN1 (Analog Input 1) is a general-purpose monitored analog input. AIN2 (Analog Input 2) is a general-purpose monitored analog input. Ground.
4
IN
MR#
5
I/O
PWR_ON
6
I/O
FS#
7
OUT
FAULT#
8
OUT
HEALTHY
9
OUT
RST#
10 11 12
IN IN GND
AIN1 AIN2 GND
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Preliminary Information
PIN DESCRIPTIONS (Cont.)
Pin Number Pin Type Pin Name Pin Description SEQ_LINK (Sequence-LinkTM) is an open drain bi-directional pin. This pin should be attached to other Sequence-Link devices, during linked operation. SEQ_LINK must be pulled high through an external pull-up resistor when multiple Sequence-Link devices are used. When the SMM766 is not used with another Sequence-Link device, SEQ_LINK should be tied directly to ground. VREF (Voltage Reference) is a bi-directional analog pin. VREF is used for Active DC Output Control and margining. VREF can be programmed to output the internal 1.25V reference. FILT_CAP (Filter Capacitor) is an external capacitor input used to filter VMX inputs. VMX (Voltage Monitor) pins are analog inputs. These pins are normally attached to the positive converter sense line, VMA through VMF. External capacitor input used to filter the VMX inputs to the 10-bit ADC, CAPA through CAPF. This provides an RC filter where R = 25k.. PUPX (Power Up Permitted) pins are programmable active high/low open drain converter enable output, PUPA through PUPF. Output voltage used to control the output of DC/DC converters, TRIMA through TRIMF. If the ADOC/margining functionality is not used on a channel the associated TRIMX pin should be grounded. TRIM_CAPX is an analog output pin used to control the output of DC/DC converters. If the ADOC/margining functionality is not used on a channel the associated TRIM_CAPX pin should be left floating. There are 6 TRIM_CAPX pins, TRIM_CAPA through TRIM_CAPF. Power supply of the part 12VIN (12 Volt Input) is a power supply input internally regulated to either 3.6V or 5.5V. VDD_CAP (VDD Capacitor) is an external capacitor input used to filter the internal supply.
13
I/O
SEQ_LINK
14 15 41,36, 31,26, 21,16 42,37, 32,27, 22,17 43,38, 33,28, 23,18 44,39, 34,29, 24,19 45,40, 35,30, 25,20 46 47 48
I/O CAP IN CAP OUT
VREF FILT_CAP VMX CAPX PUPX
OUT
TRIMX
CAP
TRIM_CAPX VDD 12VIN VDD_CAP
PWR PWR CAP
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Preliminary Information
PACKAGE AND PIN CONFIGURATION
48 LEAD TQFP
TRIM_CAPA
TRIM_CAPB
VDD_CAP
TRIMA
TRIMB
PUPB 38
48
47
46
45
44
43
42
41
40
39
SDA SCL A2 MR# PWR_ON FS# FAULT# HEALTHY RST# AIN1 AIN2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
37 36 35 34 33 32 31 30 29 28 27 26 25
CAPB
12VIN
PUPA
CAPA
VMA
VDD
VMB TRIM_CAPC TRIMC PUPC CAPC VMC TRIM_CAPD TRIMD PUPD CAPD VMD TRIM_CAPE
FILT_CAP
TRIM_CAPF
TRIMF
VREF
PUPF
CAPF
SEQ_LINK
TRIME
PUPE
CAPE
VMF
VME
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Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias....................... -55C to 125C Storage Temperature............................ -65C to 150C Terminal Voltage with Respect to GND: VDD Supply Voltage ......................... -0.3V to 6.0V 12VIN Supply Voltage ..................... -0.3V to 15.0V PUPA, through PUPF ....................... -0.3V to 15.0V All Others ................................-0.3V to VDD + 0.7V Output Short Circuit Current ............................... 100mA Lead Solder Temperature (10 s).......................... 300C Junction Temperature ......................................... .150C ESD Rating per JEDEC ....................................... 2000V Latch-Up testing per JEDEC.............................100mA
Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended.
ABSOLUTE MAXIMUM RATINGS
Temperature Range (Industrial)...........-40C to +85C (Commercial) ..............0C to +70C VDD Supply Voltage .................................. 2.7V to 5.5V 12VIN Supply Voltage1 ............................ 6.0V to 14.0V VIN ............................................................ GND to VDD VOUT ...................................................... GND to 14.0V Package Thermal Resistance (JA) 48 Lead TQFP ................................................80oC/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
Note 1 - Range depends on internal regulator set to 3.6V or 5.5V see 12VIN specification below.
RELIABILITY CHARACTERISTICS Data Retention .............................................. 100 Years Endurance..............................................100,000 Cycles
DC OPERATING CHARACTERISTIC
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max VDD 12VIN IDD I12VIN Supply voltage Supply voltage Power supply current from VDD
Internally regulated to 5.5V Internally regulated to 3.6V
2.7 10 6 3 3
5.5 14 14 5 5
Uni t V V V mA mA
All TRIM pins floating, 12VIN floating All TRIM pins floating, VDD floating TRIM sourcing maximum current TRIM sinking maximum current Depends on TRIM range of DC-DC converter 1.5 1.5
VREF/4
Power supply current from 12VIN TRIM characteristics ITRIM TRIM output current through 100 to 1.0V Margin and ADOC range
mA mA VDD V
VTRIM
TRIM_CAP characteristics TRIM output current through Max acceptable board and 1uF capacitor to ground cap leakage is 50 nA2 All other input and output characteristics ITRIM_CAP VIH Input high voltage (MR#, SDA, SCL, PWR_ON, SEQ_LINK, FS#)3 Input low voltage (MR#, SDA, SCL, PWR_ON, SEQ_LINK, FS#)3 VDD = 2.7V VDD = 5.0V VDD = 2.7V VDD = 5.0V
2086 2.1 12/13/2005 0.8 x VDD_CAP 0.7 x VDD_CAP 0.2 x VDD_CAP 0.3 x VDD_CAP
100
nA V V V V 8
VIL
Summit Microelectronics, Inc
SMM766
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max VIH Input high voltage (MR#, SDA, SCL, PWR_ON, SEQ_LINK, FS#)3 Input low voltage (MR#, SDA, SCL, PWR_ON, SEQ_LINK, FS#)3 Open drain outputs (RST#, FS#, PWR_ON, HEALTHY, FAULT#, PUPx, SEQ_LINK) Output low current Positive sense voltage Monitor threshold step size Internal temperature sensor accuracy Temperature threshold step size Internal 1.25VREF output voltage Internal VREF temperature coefficient Internal VREF accuracy External VREF voltage range External VREF=1.25V, 0.1%, total PUPx ISINK < 3ma, VSENSE < 3.5V External VREF=1.25V, 0.1%, total PUPx ISINK < 3ma, VSENSE > 3.5V Internal VREF=1.25V, total PUPx ISINK < 3ma VDD_CAP voltage at which the PUP, RST#, HEALTHY and FAULT#, FS#, PWR_ON SEQ_LINK, outputs are valid VDD_CAP rising VDD_CAP falling
Internally regulated to 3.6V Internally regulated to 5.5V Internally regulated to 3.6V Internally regulated to 5.5V
0.8 x VDD_CAP 0.7 x VDD_CAP 0.2 x VDD_CAP 0.3 x VDD_CAP
Unit V V V V V mA V mV
o o o
VIL
VOL IOL VSENSE VMONITOR tSA tMONITOR VREF VREF TC VREF ACC Ext VREF
ISINK = 1mA
Note - Total ISINK from all PUPx pins should not exceed 6mA or ADOCACC specification will be affected
0 0 +0.3 5 -3 -5 0.25 1.24 1.25
0.4 1.0
VDD_CAP
VM pin VM, AIN1/AIN2 pins Commercial temp range Industrial temp range Internal temp sensor
+3 +5
C C C
1.26 +0.25 +0.15 +0.4
VDD_CAP
V % % % V %
-40C to +85C -5C to +70C
-0.25 -0.15 -0.4 0.5 -0.2 0.1
+0.2
ADOCACC
ADOC (Active DC Output Control)/margin accuracy
-0.5 -0.5
0.3 0.3 1 2.6 2.5
+0.5 +0.5
% % V V V
VOUT_VALID
Minimum output valid voltage UVLO (Under Voltage Lockout) threshold4
UVLO
Note 1 - Range depends on internal regulator set to 3.6V or 5.5V see 12VIN specification. Note 2 - See Application Note 37 which describes the type of capacitors to use to obtain minimum leakage. Note 3 - All logic levels are derived with respect to the voltage present on VDD_CAP, when supplied from the VDD input VDD_CAP is equal to VDD, under no load. Note 4 - (100mV typ Hysteresis)
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Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) AIN1/AIN2 ADC characteristics Symbol N MC S/N DNL INL GAIN OFFSET ADC_TC IMADC IIVREF ICVREF IRVREF Parameter Resolution Missing codes Signal-to-noise Ratio Differential non-linearity Integral non-linearity Positive full scale gain error Offset error Full scale temperature coefficient Analog ADC Input Impedance VREF input current VREF input capacitance VREF input impedance
Minimum resolution for which no missing codes are guaranteed
Notes
Min 10 10
Typ
Max
Unit Bits Bits
Conversion rate = 500Hz Note 1 Note 1 Note 1 -1/2 -1 -0.5 -1
72 +1/2 +1 +0.5 +1 15 10 250 200 1
db LSB LSB % LSB PPM/ o C M nA pF k
Note 1 - The formula for the total ADC inaccuracy is: [((ADC read voltage) +/- INL)*(range of gain error)]+range of offset error
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Preliminary Information
AC OPERATING CHARICTERISTICS
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 5 and 6 Timing diagrams. Symbol Description Conditions Min Typ Max Unit TDPON = 0.64MS Programmable power-on delay TDPON = 12.5MS from restart timer expiration to -25 tDPON tDPON +25 % TDPOFF = 25MS PUPY active TDPOFF = 50MS TDPOFF = 0.64MS Programmable power-off delay -25 tDPOFF tDPOFF +25 % from VMX off to PUPY inactive TDPOFF = 12.5MS TPRTO = 0.64MS TPRTO = 25MS Programmable reset time-out delay -25 tPRTO tPRTO +25 % TPRTO = 100MS TPRTO = 200MS TSTT = OFF TSTT = 100MS Programmable sequence -25 tSTT tSTT +25 % termination timer TSTT = 200MS TSTT = 400MS Time from restart timer expiration to PUPY active Fault-triggered restart delay 2.4 s tFTRD after a fault-triggered poweroff or force-shutdown. Fault-triggered restart delay tFTRDACC -25 tFTRD +25 % accuracy Time from restart timer expiration to PUPY active Command-triggered restart delay 12.5 ms tCTRD after command-triggered power-off or force-shutdown. Command-triggered restart delay tCTRDACC -25 tCTRD +25 % accuracy Time for ADC conversion of 10-bit ADC sampling period 2.0 ms TADC all 11 channels Update period for ADOC of ADOC sampling period channels TDC_CONTROL 1.7 ms A-F Slow Margin, + 10% change in voltage with 0.1% ripple 850 ms TRIM_CAP=1F tMARGIN Margin Time from Nominal Fast Margin, + 10% change in voltage with 0.1% ripple 85 ms TRIM_CAP=1F
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Preliminary Information
I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS -100/400 kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4 Timing Diagram. Symbol fSCL TLOW THIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR_CONFIG tWR_EE Description SCL clock frequency Clock low period Clock high period Bus free time Start condition setup time Start condition hold time Stop condition setup time Clock edge to data valid Data output hold time SCL and SDA rise time SCL and SDA fall time Data in setup time Data in hold time Noise filter SCL and SDA Write cycle time config Write cycle time EE Noise suppression Configuration registers Memory array SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change
Note 1/ Note 1/ Before new transmission - Note 1/
Conditions Min 0 4.7 4.0 4.7 4.7 4.0 4.7 0.2 0.2
100kHz Typ Max 100 Min 0 1.3 0.6 1.3 0.6 0.6 0.6 3.5 0.2 0.2 1000 300 250 0 100 10 5 150 0
400kHz Typ Max 400 Units KHz s s s s s s 0.9 s s 1000 300 ns ns ns ns 100 10 5 ns ms ms
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
tR SCL tSU:SDA SDA
(IN)
tF t HD:SDA
tHIGH
t W R (For W rite O peration Only) t LOW tSU:DAT tSU:STO tBUF
tHD:DAT
tAA SDA
(OUT)
t DH
Figure 4 - Basic I2C Serial Interface Timing
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Preliminary Information
TIMING DIAGRAMS (CONTINUED)
Sequence Position PUP A tDPONA 1 2 3
VM A PUP B
tDPONB
VM B tDPONC PUP C VM C PUP D VM D
tDPOND
Figure 5 - The SMM766 cascade sequencing the supplies on and then monitoring for fault conditions.
Sequence Position PUP A VM A PUP B VM B 3 2 tDPOFFA 1
tDPOFFB
PUP C t DPOFFC VM C
PUP D
tDPOFFD
VM D
Figure 6 - The SMM766 cascade sequencing the supplies off.
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Preliminary Information
APPLICATIONS INFORMATION
DEVICE OPERATION POWER SUPPLY The SMM766 can be powered by either a 12V input through the 12VIN pin or by a 3.3V or 5.0V input through the VDD pin. The 12VIN pin feeds an internal programmable regulator that internally generates either 5.5V or 3.6V. A voltage arbitration circuit allows the device to be powered by the highest voltage from either the regulator output or the VDD input. This voltage arbitration circuit continuously checks for these voltages to determine which will power the SMM766. The resultant internal power supply rail is connected to the VDD_CAP pin that allows both filtering and holdup of the internal power supply. To ensure that the input voltage is high enough for reliable operation, an under voltage lockout circuit holds the controlled supplies off until the UVLO thresholds are met. When multiple Sequence-LinkTM devices are connected, the same VDD and/or 12VIN supplies must power all devices. MODES OF OPERATION The SMM766 has four basic modes of operation (shown in Figures 5 through 8): power-on sequencing mode, ongoing operations-monitoring mode, supply margining mode, and power-on sequencing mode. In addition, there are two features: ADOC and force-shutdown, which can be used during monitoring and margining mode. A detailed description of each mode and feature follows. ACTIVE DC OUTPUT CONTROL (ADOCTM) The SMM766 can actively control the DC output voltage of bricks or DC/DC converters that have a trim pin during monitoring and margining mode. The converter may be an off-the shelf compact device, or may be a "roll your own" circuit on the application board. In either case, the SMM766 dramatically improves voltage accuracy (down to 0.2%) by implementing closed-loop ADOC active control. This utilizes the DC-DC's "trim" pin as shown in Figure 12, or an equivalent output voltage feedback adjustment "VADJ", "FB", or "Sense" node in a user's custom circuit, Figure 13. Each of the TRIMX pins on the SMM766 is connected to the trim input pins on the power supply converters. A sense line from the channel's point-of-load connects to the corresponding VM input. The ADOC function cycles through all 6 channels (A-F) every 1.7ms making slight adjustments to the voltage on the associated TRIMX output pins based on the voltage inputs on the VMX pins. These voltage adjustments allow the SMM766 to control the output voltage of power supply converters to within 0.2% when using a 0.1% external voltage reference.
Figure 7 - Waveform shows four SMM766 channels exhibiting Sequence-on to Nominal voltage, Margin High or Low, Nominal voltage and then sequence-off Ch 1 = 3.3V DC-DC converter output (Yellow trace) Ch 2 = 2.5V DC-DC converter output (Blue trace) Ch 3 = 2.0V DC-DC converter output (Purple trace) Ch 4 = 1.8V DC-DC converter output (Green trace)
Figure 8 - Waveform shows three SMM766 channels Sequencing-on to Nominal voltage, Margin High and Low, and then sequence-off. Channel 4 shows the HEALTHY signal. Ch 1 = 3.3V DC-DC converter output (Yellow trace) Ch 2 = 2.5V DC-DC converter output (Blue trace) Ch 2 = 2.0V DC-DC converter output (Purple trace) Ch 4 = Healthy signal output (Green trace)
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APPLICATIONS INFORMATION (CONTINUED)
A pulse of current either sourced or sunk for 5s every 1.7ms, to the capacitors connected to the TRIM_CAPX pins adjusts the voltage output on the TRIMX pins. The voltages on the TRIM_CAPX pins are buffered and applied to the TRIMX pins. The voltage adjustments on the TRIMX pins cause a slight ripple of less than 1mV on the power supply voltages. The amplitude of this ripple is a function of the TRIM_CAP capacitor and the trim gain of the converter. Application Note 37 details the calculation of the TRIM_CAP capacitor to achieve a desired minimum ripple. Each channel can be programmed to either enable or disable the ADOC function. When disabled or not active, the TRIMX pins on the SMM766 are high impedance inputs. If disabled and not used, they can be connected to ground. The voltages on the TRIMX pins are buffered and applied to the TRIM_CAPX pins charging the capacitors. This allows a smooth transition from the converter powering up to its nominal voltage, to the SMM766 controlling that voltage, and to the ADOC nominal setting. The pulse of current can be increased to a 10X pulse of current until the power supply voltages are at their nominal settings by selecting the programmable Fast Margin option. As the name implies, this option decreases the time required to bring a supply voltage from the converter's nominal output voltage to the ADOC nominal, high, or low voltage setting. POWER-ON CASCADE SEQUENCING The SMM766 can be programmed to sequence on 48 supplies occupying up to 29 sequence positions. This is accomplished using the SEQ_LINK pin. Each of the 6 channels (A-F) on a SMM766 has an associated open drain PUP output that, when connected to a converter's enable pin, controls the turn-on of the converter. The channels are assigned sequence positions to determine the order of the sequence. The polarity of each of the PUPX outputs is programmable for use with various types of converters. Power-on sequencing is initiated on the rising edge of the PWR_ON pin. The SMM766 can be programmed to wait until any or all VDD, 12VIN, and Internal Temp (Internal Temperature) ADC readings are within their respective voltage threshold or temperature limits before poweron sequencing is allowed to begin. This ensures that the converters have reached their full supply voltage before they are enabled. On the rising edge of the PWR_ON pin the SMM766 will wait a power-on delay time (tDPON) for any channels in the first sequence position (position 1) and then activate the PUPX outputs for those channels. The power-on delay times are individually programmable for each channel. The SMM766 will then wait until all VMX inputs of the channels assigned to the first sequence position are above their user programmable UV1 thresholds, which is called cascade sequencing. At this point, the SMM766 will enter the second sequence position (position 2) and begin to timeout the power-on delay times for the associated channels. This process continues until all of the channels assigned to participate in the sequence have turned on and are above their UV1 threshold. Once the sequence has completed the status register indicates that all sequenced power supply channels have turned on. After the sequence has completed the SMM766 will begin the ADOC of the enabled channels. The power-on sequencing mode ends when the ADOC channels are at their nominal voltage setting. The "Ready" bit in the status register signifies that the voltages are at their set points. The programmable sequence termination timer can be used to protect against a stalled power-on sequence. This timer resets itself at the beginning of each sequence position. All channels in the sequence position must go above their UV1 threshold before the sequence termination timer times out (tSTT) or the sequence will terminate by pulling the FS# pin low, initiating a Force Shutdown. The status register contains bits indicating in which sequence position the timer timed out. This sequence termination timer has four settings of OFF, 100ms, 200ms and 400ms. While the SMM766 is in the power-on sequencing mode the RST# output is held active and the HEALTHY output is held inactive regardless of trigger sources (Figure 8). The power-off and force-shutdown trigger options are also disabled while in this mode. Furthermore, the SMM766 will not respond to activity on the PWR_ON pin or to a power-off I2C command during power-on sequencing mode. The SMM766 permits multiple supplies to occupy the same sequence position. When a sequence position is shared, each channel will be enabled after its respective power-on delay. When the last channel occupying a shared sequence position exceeds its UV1 setting the SMM766 will increment to the next
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APPLICATIONS INFORMATION (CONTINUED)
sequence position. Any unused channel should be assigned to the null sequence position. ONGOING OPERATIONS-MONITORING MODE During ongoing operations mode, the part can monitor, and actively control via ADOC, and use the forceshutdown operation if necessary. Once the power-on sequence is complete, depending on the user programmed settings; the SMM766 will either enter the ongoing operations mode directly or wait for ADOC to successfully bring all channels within their nominal values. The ongoing operations mode will end when a power-off sequence, or forceshutdown has been initiated. Once the ongoing operations mode has begun, the SMM766 continues to monitor all VMX inputs, the VDD and 12VIN inputs, and two temperature sensor inputs with a 10-bit ADC. Each of these inputs is sampled and converted by the ADC every 2ms. The ADC input has a range of 0V to four times the voltage on VREF for inputs VMA-F and the VDD input. The range is extended to 12 times VREF for the 12VIN input and is reduced to two times VREF for the AIN1 and AIN2 inputs. The SMM766 monitors internal temperature using the 10-bit ADC and the automonitor function. Two undertemperature and two over-temperature thresholds can be set, each with its own programmable threshold options and consecutive conversion, before trigger counter. Resolution is 0.25 C per bit scaled over the range of -128 C to 127.75 C. The temperature value can be acquired over the I2C bus as a 10-bit signed two's complement value. The SMM766 compares each resulting ADC conversion with two programmable 10-bit undervoltage limits (UV1, UV2) and two programmable 10bit over-voltage limits (OV1, OV2) for the corresponding input. A consecutive conversion counter is used to provide filtering of the ADC inputs. Each limit can be programmed to require 1, 2, 4 or 6 consecutive out-of-limit conversions before it is said to be in fault. One in-limit conversion will remove the fault from the threshold limit. This provides digital filtering of the monitored inputs. The ADC inputs VMA-F can use additional filtering by connecting a capacitor from the corresponding CAPX pins to ground to form an analog RC filter (R=25k). The input is considered to be in a fault condition if any of its limit thresholds are in fault. Setting an OV threshold limit to full-scale (3FFHEX), or setting a UV threshold limit to 000HEX, ensures that the limit can never be in fault. The status registers provide the real-time status of all monitored inputs. The voltage threshold limits for inputs VMA-F, VDD and 12VIN can be programmed to trigger the RST# and HEALTHY outputs as well as a Fault-Triggered forceshutdown and power-off operation when exceeded. The threshold limits for the internal temperature sensor and the AIN1 and AIN2 inputs can be programmed to assert the RST#, HEALTHY, and FAULT# output pins The HEALTHY and FAULT# outputs of the SMM766 are active as long as the monitored threshold remains in violation. The RST# output also remains active as long as the monitored threshold remains in violation. However, once the threshold violation goes away, the RST# will remain active for a programmable reset timeout period (tPRTO). The SMM766 treats Command-Triggered forceshutdown and power-off operations, those caused by I2C commands and assertion of the FS# and PWR_ON pin, differently than those caused by a Fault-Triggered forced-shutdown and power-off conditions, those caused by UV/OV violations or a sequence termination timer expiration. The mode in which either a Forced Shutdown or a power-off occurs effects how or whether the SMM766 will restart, and the number of allowable retries permited. TEMPERATURE SENSOR ACCURACY The internal temperature sensor accuracy is 5oC from -40 to +85oC. The sensor measures the temperature of the SMM766 die and the ambient temperature. If VDD is at 5V, the die temperature is +2oC and at 12V, it is +4oC. In order to calculate this difference in specific applications, measure the VDD or 12VIN supply current and calculate the power dissipated and multiply by 80oC/W. For instance, 5V and 5mA is 25mW, which creates a 2oC offset. MARGINING The SMM766 has two additional ADOC voltage settings for channels A-F, margin high and margin low. The margin high and margin low voltage settings can range from 0.3V to VDD of the converters' nominal output voltage, depending on the specified margin range of the DC-DC converter. These settings are stored in the configuration registers and are loaded into the ADOC voltage setting by margin commands issued via the I2C bus. The channel must be enabled for ADOC in order to enable margining. The margin command registers contain two bits for each channel
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APPLICATIONS INFORMATION (CONTINUED)
that decode the commands to margin high, margin low, or control to the nominal setting. Therefore, any combination of margin high, margin low, and nominal control is allowed in the margining mode. Once the SMM766 receives the command to margin the supply voltages, it begins adjusting the supply voltages to move toward the desired setting. When all channels are at their voltage setting, a bit is set in the margin status registers. Note: Configuration writes or reads of registers 00HEX to 0FHEX should not be performed while the SMM766 is margining. POWER-OFF CASCADE SEQUENCING The SMM766 performs power-off sequencing in the reverse order of power-on sequencing. Power-off cascade sequencing can be initiated by the PWR_ON pin, via I2C control or triggered by a fault condition on any of the monitored inputs. Toggling the PWR_ON pin low will initiate the power-off sequence. To enable software control of the power-off sequencing feature, the SMM766 offers an I2C command to initiate power-off sequencing while the PWR_ON pin is asserted. Furthermore, power-off sequencing can be initiated by a fault condition on a monitored input. Once power-off sequencing begins, the SMM766 will wait a power-off delay time (tDPOFF) for any channel in the last sequence position and then deactivate the PUP outputs for those channels. The power-off delay times are individually programmable for each channel. The SMM766 will then wait until all VMX inputs of the channels assigned to that sequence position are below the programmed OFF thresholds. At this point, the SMM766 will move to the next sequence position and begin to timeout the power-off delay times for the associated channels. This process continues until all of the channels in the sequence have turned off and are below their OFF thresholds. The status register reveals that all sequenced channels have turned off. The power-off sequencing mode ends when all sequenced supplies are below their OFF thresholds. The programmable sequence termination timer can be used to protect against a stalled power-off sequence. This timer resets itself at the beginning of each sequence position. All channels in the sequence position must go below their OFF threshold before the sequence termination timer times out (tSTT) or the sequence will terminate and all PUP outputs will be switched to their inactive state. This timer has four settings of OFF: 100ms, 200ms and 400ms. The sequence termination timer can be disabled separately for power-off sequencing. While the SMM766 is in the power-off sequencing mode, the RST# output is held active and the HEALTHY output is held inactive, regardless of trigger sources (Figure 8). The force-shutdown trigger option is also disabled while in this mode. Furthermore, the SMM766 will not respond to activity on the PWR_ON pin during power-off sequencing mode. FORCE SHUTDOWN The force-shutdown operation brings all PUPX outputs to their inactive state. This operation is used for an emergency shutdown when there is not enough time to sequence the supplies off. The force-shutdown operation shuts off all sequenced channels pulls the PWR_ON pin low, and waits for the supply voltages to drop below their respective OFF thresholds before beginning a restart sequence. A force-shutdown operation can be initiated by any one of four events. The first two methods for initiating a force-shutdown are always enabled. Simply taking the FS# pin low will initiate a force-shutdown operation and maintain it until the pin is brought high again. An I2C force-shutdown command allows the forceshutdown operation to be initiated via software control. This bit is cleared after all sequenced channels have dropped below their OFF voltage threshold.
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APPLICATIONS INFORMATION (CONTINUED)
LINKED OPERATION The SMM766 can be linked to multiple SequenceLink devices to create a seamless multi-channel power manager. With linked operation 8 SMM766 devices in a system can sequence up to 48 supplies within 29 sequence positions. The sequencing in this mode can be interlaced, sequencing a supply from device A, then from device B, then again from device A, etc. This extended sequencing is made possible by the inclusion of a SEQ_LINK pin. For this mode of operation, the control pins, including SEQ_LINK, PWR_ON, and FS# on each device must be tied together. In addition, the VDD and 12V supply must also be connected on all linked devices. As a consequence when multiple devices are linked together, all devices must be powered by the same supply. RESTART There are two possible conditions in which a restart sequence may be initiated. The first instance occurs when either the FS# pin is asserted or the PWR_ON pin is pulled low thus initiating a command-triggered restart. The second condition occurs when a user programmable fault triggers a force-shutdown operation or a power-off sequence thus resulting in a fault-triggered restart. In either case, the SMM766 will wait until all voltages have fallen below their user programmable OFF thresholds, after all channels are off, the PWR_ON pin will continue to be held low for a period of time dependent on the nature of the fault. When a power-off or force-shutdown condition results from a command-triggered power-off or forceshutdown, the SMM766 will automatically begin the restart procedure. When restart begins an internal timer will begin to timeout for a command-triggered Restart Delay (tCTRD) of 12.5 ms. After this time has expired the PWR_ON pin is released, allowing the power-on sequence to begin. When a power-off or force-shutdown condition results from a fault-triggered power-off or force-shutdown, the SMM766 may or may not begin the restart procedure (see PROGRAMMABLE RETRIES), if restart begins the internal timer will begin to timeout a fault-triggered Restart Delay (tFTRD) of 2.4 s before the PWR_ON pin is released allowing the power-on Sequence to begin. If the SMM766 is programmed to wait for VDD, 12VIN, or Internal Temp to be valid (above UV1 and below OV1) before power-on sequencing may commence, then this condition will be checked after the restart timer has expired and the PWR_ON pin has been released. The conditions that may lead to a Fault-Triggered restart include any channel exceeding its user programmable thresholds (OV or UV), set to trigger either a forced-shutdown or a power-off sequence. In addition, in the event that the sequence termination timer times out before a channel reaches its UV1 or OFF threshold, during sequencing, a Fault-Triggered restart occur. I2C POWER OFF CONTROL Power-on sequencing is only permitted while the PWR_ON pin is active. Once the PWR_ON pin is active and the SMM766 has entered monitoring mode, an I2C command may be issued to commence the power-off sequence. This condition will continue until an I2C "power-off clear" command is issued. PROGRAMABLE RETRIES In the event of a persistent system fault, the SMM766 may be programmed to limit the number of FaultTriggered restarts it will allow. This programmable setting ensures that the SMM766 will not enter a hiccup-mode of operation, while still reducing susceptibility to transient fault conditions. In the event of a Fault-Triggered restart the fault will be registered and internally compared to the maximum number of allowable faults. If this number is exceeded then the fault condition will be latched and the PWR_ON and FS# pins will be pulled low while the RST# output is asserted. This fault condition will remain latched until power is cycled on the SMM766, at which point the PWR_ON and FS# pins will be released, the number of faults will be reset zero, and the restart sequence will begin. The allowable programmable setting include one, three, and unlimited retries.
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APPLICATIONS INFORMATION (CONTINUED)
UNDERVOLTAGE LOCKOUT The internally filtered supply voltage as seen across VDD_CAP is edge-triggered to lock out false or nuisance signals during both the power-on and poweroff sequences. If the VDD_CAP voltage falls below 2.5V (Figure 10), an internal undervoltage lockout (UVLO) circuit will reset all internal logic. Once power has recovered above 2.6V the SMM766 will restart as if a Command-Triggered power-off had been issued.
VDD_CAP 3.6V, 5.5V 2.6V 2.5V
UVLO (Internal)
Figure 10 - Timing Sequence recovering from a VDD_CAP Power `Brown-Out'
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APPLICATIONS INFORMATION (CONTINUED)
Figure 11 - SMM766 Distributed power applications schematic. The accuracy of the external reference (U10) sets the accuracy of the ADOC function. Total accuracy with a 0.1% external reference is 0.2%
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Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and WindowsTM GUI software. It can be ordered on the website or from a local representative. The SMX3200 programming Dongle/cable interfaces directly between a PC's parallel port and the target application. The device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMM766 via the programming Dongle and cable. An example of the connection interface is shown in Figure 15. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application.
D1 1N4148 VDD_CAP
Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector. Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND
SMM766
MR# SDA SCL
10 8 6 4 2
9 7 5 3 1
0.1F
GND
Figure 12 - SMX3200 Programmer I2C serial bus connections to program the SMM766. Note that the MR# pin does not need to be connected to pin 6 for programming purposes.
The latest revisions of all software and an application brief describing the SMX3200 is available from the website at:
http://www.summitmicro.com/tech_support/program_kit/SMX3200.htm
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I2C PROGRAMMING INFORMATION
SERIAL INTERFACE Access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standard 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is a clock input. Data is clocked in on the rising edge of SCL and clocked out on the falling edge of SCL. All data transfers begin with the MSB. During data transfers SDA must remain stable while SCL is high. Data is transferred in 8-bit packets with an intervening clock period in which an Acknowledge is provided by the device receiving data. The SCL high period (tHIGH) is used for generating Start and Stop conditions that precede and end most transactions on the serial bus. A high-to-low transition of SDA while SCL is high is considered a Start condition while a low-to-high transition of SDA while SCL is high is considered a Stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. The address byte is comprised of a 4-bit device type identifier SA[3:0] (slave address) and a 3-bit bus address BA[2:0]. The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMM766. The device type identifier for the memory array is generally set to 1010BIN following the industry standard for a typical nonvolatile memory. There is an option to change the identifier to 1011BIN allowing it to be used on a bus that may be occupied by other memory devices. The configuration registers are grouped with the memory array and thus use 1010BIN or 1011BIN as the device type identifier. The command and status registers as well as the 10-bit ADC are accessible with the separate device type identifier of 1001BIN. The bus address bits BA[1:0] are programmed into the configuration registers. Bus address bit BA[2] can be programmed as either 0 or biased by the A2 pin. The bus address accessed in the address byte of the serial data stream must match the setting in the SMM766 and on the A2 pin.
Any access to the SMM766 on the I2C bus will temporarily halt the monitoring function. This does not affect the ADOC function, which will continue functioning and control the DC outputs. This is true not only during the monitor mode, but also during power-on and power-off sequencing when the device is monitoring the channels to determine if they have turned on or turned off. The SMM766 halts the monitor function from when it acknowledges the address byte until a valid stop is received. WRITE Writing to the memory or a configuration register is illustrated in Figures 13, 14, 15, 17 and 19. A Start condition followed by the address byte is provided by the host; the SMM766 responds with an Acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMM766 responds with an acknowledge; the host then clocks in on byte of data. For memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. After the last byte is clocked in and the host receives an Acknowledge, a Stop condition must be issued to initiate the nonvolatile write operation. READ The address pointer for the configuration registers, memory, command and status registers and ADC registers must be set before data can be read from the SMM766. This is accomplished by a issuing a dummy write command, which is simply a write command that is not followed by a Stop condition. The dummy write command sets the address from which data is read. After the dummy write command is issued, a Start command followed by the address byte is sent from the host. The host then waits for an Acknowledge and then begins clocking data out of the slave device. The first byte read is data from the address pointer set during the dummy write command. Additional bytes can be clocked out of consecutive addresses with the host providing an Acknowledge after each byte. After the data is read from the desired registers, the read operation is terminated by the host holding SDA high during the Acknowledge clock cycle and then issuing a Stop condition. Refer to Figures 16, 18 and 21 for an illustration of the read sequence.
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I2C PROGRAMMING INFORMATION (CONTINUED)
The word address must be set each time the memory WRITE PROTECTION is accessed. Memory writes and reads are shown in The SMM766 powers up into a write protected mode. Figures 19, 20 and 21. Writing a code to the volatile write protection register can disable the write protection. The write protection COMMAND AND STATUS REGISTERS register is located at address 87HEX of slave address The command and status registers are located at 1001BIN. slave address 1001BIN. Writes and reads of the command and status registers are shown in Figures Writing 0101BIN to bits [7:4] of the write protection 22 and 23. register allow writes to the general-purpose memory while writing 0101BIN to bits [3:0] allow writes to the ADC CONVERSIONS configuration registers. The write protection can reAn ADC conversion on any monitored channel can be enable by writing other codes (not 0101BIN) to the write performed and read over the I2C bus using the ADC protection register. Writing to the write protection read command. The ADC read command, shown in register is shown in Figure 13. Figure 24, starts with a dummy write to the 1001BIN CONFIGURATION REGISTERS slave address. Bits [6:3] of the word address byte are used to address the desired monitored input. Once The majority of the configuration registers are grouped the device acknowledges the channel address, it with the general-purpose memory located at either begins the ADC conversion of the addressed input. slave address 1010BIN or 1011BIN. Bus address bits BA[2:1] are programmable. The bus address bit BA[0], This conversion requires 225s to complete. During however, is used to differentiate the general-purpose this conversion time, acknowledge polling can be memory from the configuration registers and should be used. The SMM766 will not acknowledge the address set to 1BIN when accessing the configuration registers. bytes until the conversion is complete. When the Bus address bit BA[2] can be programmed as a conversion has completed, the SMM766 will "virtual 0" or biased by the A2 pin. acknowledge the address byte and return the 10-bit conversion along with a 4-bit channel address echo. An additional configuration register is located at address 84HEX of slave address 1001BIN. GRAPHICAL USER INTERFACE (GUI) Writing and reading the configuration registers is Device configuration utilizing the Windows based shown in Figures 14, 15, 16, 17, and 18 SMM766 graphical user interface (GUI) is highly recommended. The software is available from the Note: Configuration writes or reads of registers 00HEX Summit website at: to 0FHEX should not be performed while the SMM766 is (http://www.summitmicro.com/tech_support/tech.htm# margining. GUI. GENERAL-PURPOSE MEMORY Using the GUI in conjunction with this datasheet The 2k-bit general-purpose memory is located at simplifies the process of device prototyping and the either slave address 1010BIN or 1011BIN. Bus address interaction of the various functional blocks. A bits BA[2:1] are programmable. The bus address bit programming Dongle (SMX3200) is available from BA[0], however, is used to differentiate the generalSummit to communicate with the SMM766. The purpose memory from the configuration registers and Dongle connects directly to the parallel port of a PC should be set to 0BIN when accessing general purpose and programs the device through a cable using the I2C memory. Bus address bit BA[2] can be programmed bus protocol. as a "virtual 0" or biased by the A2 pin. Slave Address Bus Address Register Type 1001BIN 1010BIN or 1011BIN BA2 BA1 BA0 Write Protection Register, Command and Status Registers, One Configuration Register, ADC Conversion Readout 2-k Bits of General-Purpose Memory Configuration Registers
BA2 BA1 0 BA2 BA1 1
Table 1 - Address bytes used by the SMM766.
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I2C PROGRAMMING INFORMATION (CONTINUED)
Master
S T A R T 1 0 0 1
Bus Address B A 2 B A 1 B A 0
Configuration Register Address = 87HEX W A C K 1 0 0 0 0 1 1 1 A C K 0 1 0
Data = 55HEX 1 0 1 0 1 A C K 5HEX Unlocks General Purpose EE 5HEX Unlocks Configuration Registers
S T O P
Slave
8HEX Write Protection Register Address
7HEX
Figure 13 - Write Protection Register Write
S T A R T 1 Slave 0 1 S A 0 S T O P D 2 D 1 D 0 A C K
Master
Bus Address B A 2 B A 1 1 W A C K C 7 C 6
Configuration Register Address C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data D 4 D 3
Figure14 - Configuration Register Byte Write
S T A R T 1 Slave 0 1 S A 0
Master
Bus Address B A 1 B A 1 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data D 4 D 3 D 2 D 1 D 0 A C K
1
Master D 7 Slave D 6 D 5
Data (2) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5
Data (16) D 4 D 3 D 2 D 1 D 0 A C K
S T O P
Figure 15 - Configuration Register Page Write
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I2C PROGRAMMING INFORMATION (CONTINUED)
S T A R T 1 Slave 0 1 S A 0 S T A R T C 1 C 0 A C K 1 0 1 S A 0
Master
Bus Address B A 2 B A 1 C 7 A C K C 6
Configuration Register Address C 5 C 4 C 3 C 2
Bus Address B A 2 B A 1
1
W
1
R A C K
Master D 7 Slave D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0
A C K D 7 D 6 D 5 D 2 D 1 D 0
A C K D 7 D 6 D 5
Data (n) D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
Figure 16 - Configuration Register Read
S T A R T 1 Slave 0 0 1
Master
Bus Address B A 2 B A 1 B A 0 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data D 4 D 3 D 2 D 1 D 0 A C K
S T O P
Figure 17 - Configuration Register with Slave Address 1001BIN Write
S T A R T 1 Slave 0 0 1 S T A R T C 1 C 0 A C K 1 0 0 1
Master
Bus Address B A 2 B A 1 B A 0 C 7 A C K C 6
Configuration Register Address C 5 C 4 C 3 C 2
Bus Address B A 2 B A 1 B A 0
W
R A C K
Master D 7 Slave D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0
A C K D 7 D 6 D 5 D 2 D 1 D 0
A C K D 7 D 6 D 5
Data (n) D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
Figure 18 - Configuration Register with Slave Address 1001BIN Read
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SMM766
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S T A R T 1 Slave 0 1 S A 0 S T O P D 2 D 1 D 0 A C K
Master
Bus Address B A 2 B A 1 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data D 4 D 3
0
Figure 19 - General Purpose Memory Byte Write
S T A R T 1 Slave 0 1 S A 0
Master
Bus Address B A 2 B A 1 C 7 A C K C 6
Configuration Register Address C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0 A C K
0
W
Master D 7 Slave D 6 D 5
Data (2) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5
Data (16) D 4 D 3 D 2 D 1 D 0 A C K
S T O P
Figure 20 - General Purpose Memory Page Write
S T A R T 1 Slave 0 1 S A 0 S T A R T C 1 C 0 A C K 1 0 1 S A 0
Master
Bus Address B A 2 B A 1 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2
Bus Address B A 2 B A 1
0
0
R A C K
Master D 7 Slave D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0
A C K D 7 D 6 D 5 D 2 D 1 D 0
A C K D 7 D 6 D 5
Data (n) D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
Figure 21 - General Purpose Memory Read
Summit Microelectronics, Inc
2086 2.1 12/13/2005
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SMM766
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S T A R T 1 Slave 0 0 1 S T O P D 2 D 1 D 0 A C K
Master
Bus Address B A 2 B A 1 B A 0 C 7 A C K C 6
Command and Status Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data D 4 D 3
Figure 22 - Command and Status Register Write
S T A R T 1 Slave 0 0 1 S T A R T C 1 C 0 A C K 1 0 0 1
Master
Bus Address B A 2 B A 1 B A 0 C 7 A C K C 6
Command and Status Register Address C 5 C 4 C 3 C 2
Bus Address B A 2 B A 1 B A 0
W
R A C K
Master D 7 Slave D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0
A C K D 7 D 6 D 5 D 2 D 1 D 0
A C K D 7 D 6 D 5
Data (n) D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
Figure 23 - Command and Status Register Read
S T A R T 1 Slave 0 0 1 S T A R T 0 0 0 A C K 1 0 0 1
Master
Bus Address B A 2 B A 1 B A 0
Channel Address C H 3 C H 2 C H 1 C H 0
Bus Address B A 2 B A 1 B A 0
W A C K
0
R N A C K
Master
S T A R T 1 0 0 1
Bus Address B A 2 B A 1 B A 0
Channel Address Echo C H 3 C H 2 C H 1 C H 0 D 9 D 8
A C K 0 D 7
10-Bit ADC Data D 6 D 5 D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
R A C K
0
Slave
Figure 24 - ADC Conversion Read
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SMM766
Preliminary Information
DEFAULT CONFIGURATION REGISTER SETTINGS - SMM766FC-251
Register R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF R10 R11 R12 R13 R14 R15 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R3A R3B R3C R3D R3E
RC1
Contents FD 84 0E 00 0E 62 0E C7 0F 55 0B 20 FF 00 04 08 7F 7F 7F 7F 7F 7F 7F 6E 0E DA 0E 46 0E 80 0F 08 0F D9 00 12 50
Register R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R4A R4B R4C R4D R4E R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R8A R8B R8C R8D R8E R8F R90 R91 R92 R93 R94 R95
Contents FD 9D 0E 2D 0E A2 0F 20 0F B4 0B 69 00 12 50 4A 7B 82 66 2A CD 12 E1 49 D7 81 C3 2A 29 12 3D 49 85 81 71 29 D7
Register R96 R97 R98 R99 R9A R9B R9C R9D R9E R9F RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RAA RAB RAC RAD RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RBA RBB RBC
Contents 11 EC 49 85 81 71 29 9A 11 AE 49 0A 80 F6 29 5C 11 71 48 CD 80 B8 29 1F 11 33 02 52 03 FF 03 FF 02 23 02 23 03
Register RBD RBE RBF RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RCA RCB RCC RCD RCE RCF RD0 RD1 RD2 RD3 RD4 RD7 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 REA REB
Contents E0 03 E0 03 38 03 38 01 90 01 90 00 00 00 00 03 FF 03 FF 00 00 00 00 03 D8 00 3D 00 3D 00 3D 00 3D 00 3D 00 3D
The default device ordering number is SMM766FC-251. It is programmed with the register contents as shown above and tested over the commercial temperature range with a VREF setting of 1.25V. Other standard external VREF voltage settings that can be specified and tested are values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300. The value is derived from the customer supplied hex file. New device suffix numbers are assigned to non-default requirements. If other VREF values are required, please contact a Summit Microelectronics Sales Representative.
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SMM766
Preliminary Information
PACKAGE
48 PIN TQFP PACKAGE
0.354 (9.00) 0.276 (7.00) BSC (A) BSC (B) Inches (Millim eters)
0.02 (0.5)
BSC
0.007 - 0.011 (0.17 - 0.27)
DETAIL "A"
(B) (A)
Ref Jedec M S-026
0.037 - 0.041 0.95 - 1.05 Pin 1 Indicator 0.039 (1.00)
Ref
0.047 MAX. (1.2)
0 o Min to 7 o Max
A
B
0.002 - 0.006 (0.05-0.15)
0.018 - 0.030 (0.45 - 0.75)
DETAIL "B"
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SMM766
Preliminary Information
PART MARKING
SUMMIT SMM766F Annn
Pin 1
Summit Part Number
xx
Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use)
AYYWW
Date Code (YYWW)
Lot tracking code (Summit use) Part Number suffix (Contains Customer specific ordering requirements)
Drawing not to scale
Product Tracking Code (Summit use)
ORDERING INFORMATION Summit Part Number SMM766 F C nnn Part Number Suffix (see page 28)
Specific requirements are contained in the suffix such as Hex code, Hex code revision, etc. The calibrated VREF voltage settings are standard values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300
Temp Range Package C=Commercial F=48 Lead TQFP Blank=Industrial
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SMM766
Preliminary Information
Terms and Definitions
Fault-Triggered This term refers to either a power-off or force-shutdown operation. When a UV, OV, or sequence termination condition trigger a power-off or force-shutdown a fault triggered poweroff or force-shutdown is said to occur. This sets the restart delay at 2.4s, and can limit the number of allowable retries. This term has no correlation to the FAULT pin. This term refers to either a power-off or force-shutdown operation. When either the FS# or PWR_ON pin is asserted or an I2C command is issued a Command-Triggered power-off or force-shutdown is said to occur. This sets the restart delay at 12.5ms, and will not limit the number of allowable retries. ADOC (Active DC Output Control) is a proprietary secondary closed loop compensation control, used to maintain output voltages to 0.2%. Power-off sequencing refers to cascaded power-off sequencing unless explicitly noted. Cascaded power-off sequencing refers to a feedback based supply termination in which each channel in the previous sequence position is monitored, and the monitored voltage must fall below a programmable OFF threshold before the next sequence position is allowed to turn off. Channels in the same sequence position are not capable of Cascaded power-off sequencing. Power-off sequencing refers to cascaded power-off sequencing unless explicitly noted. Cascaded power-off sequencing refers to a feedback based supply termination in which each channel in the previous sequence position is monitored, and the monitored voltage must fall below a programmable OFF threshold before the next sequence position is allowed to turn off. Channels in the same sequence position are not capable of Cascaded power-off sequencing. When all supplies are immediately disabled without regard to sequence position. When more than one SMM766 or SMM766 derivatives are connected creating a seamless multi-channel network. Programmed Under Voltage threshold for monitored channels and supplies Programmed Over Voltage threshold for monitored channels and supplies Undervoltage Lockout. Prevents voltage at VDD or 12VIN pin from powering the SMM766 until proper operating voltages have been reached. The ability to change the nominal output voltage by use of trim pin. Analog to Digital Converter. Converts analog voltage to digital voltage. SMM766 represents all measured voltages by 10-bit digital reading. The number of times the SMM766 will restart after a Fault-Triggered power-off or forceshutdown. When the SMM766 begins power on sequencing, includes initial power-on sequence. Delay from restart timer expiration to PUPY pin active Programmable delay from VMX off to PUPY inactive When a supply fails to reach its programmed UV, or OFF, threshold before expiration of internal timer. When any quantity including temperature, and voltage is converted to a digital value by the ADC and compared against a user programmable setting. Graphical user interface. Program that reads from and writes to non-volatile registers on the SMM766 and displays results in accordance to register function.
Command-Triggered
ADOCTM Power-off
Power-on
Force-shutdown Sequence-LinkTM UV OV UVLO Margin ADC Retries Restart Power-on delay Power-off delay Sequence Termination Monitoring GUI
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Preliminary Information
NOTICE
NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. Revision 2.1 - This document supersedes all previous versions. Data Sheet updates can be accessed by "right" or "left" mouse clicking on the link:
http://www.summitmicro.com/prod_select/summary/smm766.htm
Device Errata sheets can be accessed by "right" or "left" mouse clicking on the link: http://www.summitmicro.com/errata/SMM766 SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. (c) Copyright 2005 SUMMIT MICROELECTRONICS, Inc. ADOC
TM
PROGRAMMABLE ANALOG FOR A DIGITAL WORLDTM
and Sequence-Link
TM
are registered trademarks of Summit Microelectronics Inc., I2C is a trademark of Philips Corporation.
Summit Microelectronics, Inc
2086 2.1 12/13/2005
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